application note semiconductor group 294 sda 9257: a generator chip as frequency synthesizer for tv applications color tv sets with the siemens featurebox are notable for their flicker-free picture and convenient functions such as frame freeze picture-in-picture, 9-in-1 picture and noise reduction. following development of the sda 9205-2 triple a/d converter and sda 9257 clock sync generator, television sets with analog processing of the video signal can now enjoy all the advantages of the digital featurebox. the sda 9257 can also be used as a general purpose video pulse generator and frequency synthesizer. using the clock sync generator (csg), the triple adc and an analog color decoder (e.g. tda 4555), analog tv frontends can now be designed that produce all the picture signals, sync pulses and clock pulses required by the featurebox ( figure 1 ). the csg works with all standards for composite video blanking signals (cvbs), such as 50 hz, 60 hz, pal, ntsc and secam, and is optimized in its clock and sync generation for different tv and vcr sources. frequency synthesizer used as a frequency synthesizer, the csg generates frequencies between approximately 10.3 and 37.7 mhz at its clock outputs. the required frequency can be set in very fine increments by a 16-bit value on the i 2 c bus and can also be crystal-controlled with an external crystal as a reference ( figure 2 ).
application note semiconductor group 295 figure 1 featurebox environment with analog color decoder figure 2 clock sync generator (csg) as frequency synthesizer
application note semiconductor group 296 automatic clamping the cvbs-input signal can be clamped by the csg automatically. if a video signal multiplexer heads the circuit, clamping will be made there and the csg provides the multiplexer with the necessary clamping pulses. the csg can also be supplied with a sync or a ys signal; the clamping then has to be disabled. by means of clamping, the cvbs signal with an unknown dc component is shifted in its dc position so that its sync signal component is within the driving range of the internal a/d converter and the horizontal pll (hpll) can securely lock onto the h pulses. the clamping algorithm covers four phases and is started by the power-on: l phase 1: a transistor switch clamps the cvbs to the lower adc-reference voltage of 0 v for the duration of six tv lines. l phase 2: a transistor switch then clamps the cvbs to 5 v every time the underflow bit of the adc appears for longer than 1.1 m s. following this phase it is certain that a major part of the sync signal component is within the driving range of the adc. from phase 3 onward, a constant check is made to ensure that the cvbs goes below the mean value of the adc-driving range at least once per line. if not, clamping phase 1 is started again. underflow is also monitored: if the cvbs goes below the lower adc-driving limit by more than 0.1 v and for longer than 1.1 m s, a switch briefly clamps to 5 v. l phase 3: the switch clamps to 0 v with a pulse that lags approx. 1 m s behind the h-sync leading edge. phase 4 is initiated and maintained when the hpll is locked to the cvbs for better than approx. 600 ns. l phase 4: the switch clamps to 0 v with a pulse coupled direct to the hpll that appears in the first half of the h-sync pulse.
application note semiconductor group 297 figure 3 block diagram of clock sync generator clock generation clock generation basically consists of three parts ( figure 3 ): l the digital horizontal phase-locked loop (hpll) generates a digital value that is proportional to the frequency of the clock line-locked to the cvbs. l by means of a discrete timing oscillator (dto) followed by a sine coder and dac, a line-locked clock signal is produced whose frequency is a quarter of the output clock frequency. l an analog pll quadruples this frequency and minimizes the jitter. this configuration enables separate optimization of the lock-in response and clock jitter. horizontal phase-locked loop figure 4 illustrates the hpll. after the cvbs has been a/d-converted with 7 bits resolution and 27 mhz, there follows an fir lowpass filter with a cutoff frequency of 1 mhz to improve the snr, eliminate the chroma component and produce defined edge steepness of the sync pulses (which is necessary for accurate digital measurement of the phase difference). subtraction of the black level in the sync slicer leaves just the sync signal component of the cvbs at the output of the amplitude separator. comparison of the position of the sync edges with the pixel counter, which represents the phase of the hpll, provides a rough value for the phase difference. integration of the sync edge during a window defined by the pixel counter produces a precise value for the phase difference if the hpll is already phased in accurately enough.
application note semiconductor group 298 the phase difference is applied to a non-linear pl filter, whose coefficients are determined both by the instantaneous phase difference and by the mode (tv or vcr) set on the i 2 c bus. the output of the pl loop filter is the increment of a discrete timing oscillator (dto) and thus determines the clock frequency of the chip and the device outputs. the momentary black level and sync level are constantly measured on the digital sync signal. the method of measurement is different for large and small phase differences. the value measured for the black level is fed to the black-level control. this produces the black level that is subtracted from the digitized cvbs in the sync slicer. from the black level and the measured sync signal, the threshold control forms a sync cutoff threshold with the aid of which coarse measurement of phase difference is made and the vertical pulse is separated. figure 4 the digital horizontal pll generates a digital value if the digital sync signal in the hpll goes below the sync cutoff threshold, a counter is incremented; otherwise it is decremented. the reading of the counter is thus a measure of the length of the sync pulse. during the first main tail of the vertical blanking interval, the counter exceeds a given value and thus detects a vertical pulse in the cvbs. this kind of vertical pulse separation is largely the same as the analog principle. this pulse goes to vertical sync processing. if there is no cvbs on the input of the csg, the hpll will ensure that the clock frequency is set to the nominal value. this makes sure in the tv set that the high voltage for the tube generated by the csg pulses will not increase.
application note semiconductor group 299 discrete timing oscillator the dto ( figure 5 ), consisting of an adder and a register with crystal-referenced timing, generates a sawtooth signal with a frequency proportional to the value of the increment and the crystal frequency. after recoding in a rom, d/a conversion and bandpass filtering, the result is a sinusoidal analog signal that is converted into a clock signal in the schmitt trigger (st). this clock frequency is only a quarter of the device output clock frequency so that the sampling theorem is fulfilled, but not with too high a crystal frequency (sampling frequency). figure 5 the discrete timing oscillator consists of an adder and register; it generates a sawtooth signal analog phase-locked loop the analog pll quadruples the frequency. appropriate selection of the attenuation and natural frequency produces a marked reduction in high-frequency clock jitter, regardless of the low- frequency transient response (and jitter) of the hpll. furthermore, the resistances and capacitances of the analog loop filter are low and can therefore be integrated. vertical sync processing vertical sync processing detects the lines per field and reduces interference of the vertical pulse. the line count, using the vertical pulse separated from the cvbs in the hpll, first detects whether the line number per field is greater or smaller than 287. by means of different settings of a measuring window (wide or narrow) on the i 2 c bus, four ranges can be identified for the line count, and these can also be read out via the i 2 c bus. integrated averaging and hysteresis ensure that these ranges are properly detected even when vcr signals fluctuate in their line count or broadcast signals are affected by heavy noise. the line count also produces (on the i 2 c bus) a field bit. this toggles on each change of field, but it is always set to 0 when the separated vertical pulse appears within the first half of the line and also within the selected window when the vertical interference reduction is activated. in other words, this bit is always 0 during the first field.
application note semiconductor group 300 when the vertical line interference reduction is activated, the vertical pulse from the hpll is only allowed to pass within the selected window and appears as a pulse on the vs output of the device. two different window widths (optimized for vcr and broadcast signals) can be set for 525-line or 625-line standards. in the occasional absence of vertical pulses from the hpll, a vs pulse is triggered at the latest after 340 or 288 lines. if a flywheel is also activated, missing v pulses are continuously added every 312.5 or 262.5 lines. the vs pulse can also be generated in a free wheeling manner, i.e. independent of the cvbs input, and for both 312.5 and 262.5 lines per field. in what is called terminal mode, free-wheeling generation of the vs takes place with 312.0 or 262.0 lines per field. so if the cvbs contains a lot of noise, missing v pulses can be added by activating the flywheel and v-interference pulses can blanked by activating the interference reduction. each of these can be activated independently of the other. bottom flutter elimination the momentary frequency of the output clock pulses can be frozen in a line band about the vertical blanking interval to suppress bottom flutter in vcr mode. the beginning of the band before the v pulse and its duration can be set on the i 2 c bus. pulse generation the csg supplies different sync pulses generated with the aid of the pixel counter in the hpll. so these have clock-synchronized edges and are free of horizontal interference. l the position of the horizontal pulse hs can be set across the entire line by means of the i 2 c bus, and the position of the h1 and h2 pulses can be set in a suitable band about the line blanking interval. as h1 and h2 can be used for external clamping, their width is also adjustable. l in the case of the sandcastle or super-sand-castle pulse (depending on the pin function selected), there is no burst key. this has to be inserted externally because of its 11-v ievel. for this purpose, the inverted burst pulse is available on a further pin. the location of the sandcastle and burst pulse, which are in a fixed relation, is adjustable. l the composite sync pulse is derived directly from the filtered cvbs by means of the sync cutoff threshold formed in the hpll. this calls for a cvbs input signal and cannot be varied in position. l the blanking signal bln for the featurebox can be adjusted in position and width.
application note semiconductor group 301 abbreviations adc analog/digital converter cvbs composite video blanking signal csg clock sync generator dac digital/analog converter ddc digital deflection controller dto discrete timing oscillator fb, fbx featurebox hpll horizontal pll i 2 c bus serial data bus for entertainment electronics mux multiplexer ntsc national television system committee (us standard) pal phase alternating line (german standard) pll phase-locked loop rgb red, green, blue component signals rom read-only memory secam squentielle couleur a mmoire (french standard) snr signal/noise ratio st schmitt trigger vs vertical sync pulse references [1] hass, m.; draxelmayr, d.; kuttner, f.; zojer, b.: a monolithic triple 8-bit cmos video coder. ieee transactions of consumer electronics, vol. 36, no. 3, august 1990 [6] kramer, r.: bus controlled clock generator. ieee transactions of consumer electronics, vol. 37, no. 3, august 1991
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